import param_P::P;

module V2_1(
input wire[7:0]                 a,
input wire[7:0]                 b,
input wire[P-1:0]					e,
input wire[P-1:0]					f,
input wire[P-1:0]					g,
input wire        				d,
input wire            			reset,
input wire               		clk,

output reg         			out,
//output wire [7:0]				h,
output reg [(P*2)-1:0]				data_out,
output wire[15:0]                c);

reg[(P*2)-1:0]					h;
reg[(P*2)-1:0]					i;
reg[(P*2)-1:0]					j;

//TASK2:
	
assign c                     =a*b;

//////////////////

always@(posedge clk)
begin: TASK3
	out <=d;
end

/////////////////////

always@(negedge reset or posedge clk)
begin: TASK4
	if(!reset)
	begin
		h			<= 0;
		i			<= 0;
		j			<= 0;
		data_out	<= 0;
	end
	else
	begin
		h			<=e*f;
		i			<=g;
		j			<=i;
		data_out	<=h+i;
	end
end

endmodule                              